Currently, plasma vapor deposition (PVD) titanium (Ti), atomic layer deposition (ALD) titanium nitride (TiN) with chemical vapor deposition (CVD) tungsten (W) are industry standards for S/D contract fill for sub-20 nm nodes. A known flow for contact metallization is depicted in FIG. 1A. In step 101, a contact (referred to as a trench contact (TT)) is formed through an interlayer dielectric layer (ILD) down to S/D regions by reactive ion etching (RIE). In step 103, a silicon oxycarbide (SiOC) layer is formed on side surfaces of the TT. An argon (Ar) sputter process is then performed in step 105 followed by a silicon (Si) implantation into the TT by angled pre-amorphous implantation (PAI) in step 107. In step 109, a portion of the TT is removed by Ar sputtering, which is then followed by a remote plasma assisted dry etch process, e.g., SiCoNi™, to remove native oxide on the bottom of the trench prior to silicide formation.
In steps 111 through 117, nickel silicide (NiSi) is formed in the TT on the S/D region. In step 111, nickel platinum (Ni1-xPtx), where x ranges from 5 to 50 atomic weight (at. wt.) %, is deposited in the TT to a thickness of 150 angstroms (Å) to 200 Å by PVD and TiN is also deposited in the TT to a thickness of 32 Å. In steps 113 and 115, a rapid thermal anneal (RTA) is performed, which is then followed by a strip process. In step 117, a second RTA (Flash or laser-based surface anneal (LSA)) is performed, then followed by a second strip process.
In steps 119 through 127, the TT is filled with a contact metal. In step 119, an Ar sputtering is performed. In step 121, a Ti layer is deposited by PVD in the TT to a thickness of 50 Å to 60 Å. Thereafter, in step 123, a second layer of TiN is formed in the TT by atomic layer deposition (ALD). The second layer of TiN is formed to a thickness of 32 Å. In step 125, the remainder of the TT is filled with W, for example to a thickness of 1500 Å to 2000 Å. In step 127, the W is planarized, e.g., by chemical mechanical polishing (CMP).
FIGS. 1B through 1F schematically illustrate the current contact metallization flow in middle-of-line (MOL) process discussed above to form a TT 131 with respect to FIG. 1A. Adverting to FIG. 1B, a SiOC layer 129 is formed on side surfaces of a TT 131. An Ar sputter process is then performed followed by a Si implantation into the TT by angled PAI, forming the Si PAI layer 133. A portion of the TT 131 is removed by Ar sputtering, which is then followed by a SiCoNi™ etch to clean the bottom of the TT 131 prior to silicide formation. Next, a NiPt layer 135 is deposited in the TT, for example, to a thickness of 150 Å, and a TiN layer 137 is also deposited in the TT, for example, to a thickness of 50 Å.
Adverting to FIG. 1C, a RTA is performed which produces a NixSiy layer 139 and an unreacted NiPt layer 135′. The TiN layer 137 is then stripped, as depicted in FIG. 1D. After the TiN layer 137 is stripped, a second RTA is performed, which forms a NiSi layer 139′, as depicted in FIG. 1E. Thereafter, the NiPt layer 135 is stripped. Adverting to FIG. 1F, a Ti layer 141 is deposited by PVD in the TT 131 to a thickness of 50 Å to 60 Å. Next, a TiN layer 143 is formed in the TT 131 by ALD. Thereafter, the remainder of the TT 131 is filled with a W layer 145. Consequently, a void 147 is formed as a result of necking.
As technology scaling requires contact critical dimension (CD) continuously reduced with high aspect ratios, contact etching, contact pre-clean prior to silicide formation as well as metal filling in contacts becomes more difficult. The contact etching needs to have minimum lateral etching and high selectivity so that the contact CD is not “blown-up,” which may lead to TT to gate shorts and degradation of transistor overlap and effective capacitance. Furthermore, inadequate clean (pre-clean) prior to silicide formation on the bottom of TT hinders silicide formation which in-turn leads to the TT being open due to silicide missing or high resistance silicide-S/D contacts due to thin silicide. However, increasing pre-clean would lead to further CD blow-out of TT. In addition, W-gapfill issues in the contact module lead to W-voids, line voids, and missing contacts, which are a major device and yield inhibitor. CVD W films (bulk) also have a large grain structure, which makes gap-fill and polishing challenging. Further, improper W fill in the contacts can lead to increased resistance of contacts, i.e., a serious degradation of yield and device performance.
A need therefore exists for methodology enabling an integration scheme for maintaining small contact CD by minimizing lateral contact etching, enhancing NiSi formation, and improving W-gapfill, and the resulting device.